1. Field of the Invention
This invention relates to a process for forming an integrated circuit structure with at least one layer of copper interconnects on a silicon substrate. More particularly, this invention relates to a process for the abrasive removal of copper deposited on the back surface of the substrate, prior to further high temperature processing of the substrate.
2. Description of the Related Art
In the formation of integrated circuit structures of ever decreasing size, and increasing speed or response, with adequate current carrying capabilities, the use of copper as a replacement interconnect material for aluminum has become of interest because of the lower resistance of copper and resulting ability to carry higher current.
However, the replacement of aluminum interconnects or wiring with copper requires changes in processing. An aluminum layer may be patterned to form interconnects by a plasma etch which, for example, may form a volatile aluminum chloride compound which may then be removed as a gas from the etch chamber. However, the difficulty in forming volatile copper compounds has resulted in the need to use other methods of patterning a layer of copper interconnects.
One process for forming copper interconnects which has been proposed, is to form a pattern of trenches in an insulation layer conforming to the desired pattern of copper interconnects. A blanket deposition of copper is then made over the insulation layer and in the trenches. A subsequent chemical/mechanical polishing step then removes the copper from the surface of the insulation layer, leaving the desired pattern of copper interconnects in the trenches.
While the sputtering or physical vapor deposition (PVD) of copper would be the deposition process of choice for filling the trenches with copper, due to ease of spatial control of the deposited area, sputtering does not adequately fill narrow trenches (e.g., trenches having a width less than 0.75 microns). Therefore, to provide for adequate filling of the trenches, it has been proposed to either deposit the copper by chemical vapor deposition (CVD) or by electroplating.
However, both of these latter deposition processes can result in undesirable deposition of copper on the back surface of the substrate, as well as on the desired areas on the front side of the substrate, e.g., in the trenches in the insulation layer. Since copper rapidly diffuses through silicon at high temperatures, such as those temperatures incurred during subsequent processing of the structure (e.g., during annealing or deposition of a further insulation layer), it is imperative that copper not be permitted to accumulate on the back surface of the substrate, since the presence of copper in the silicon substrate can degrade the performance of integrated circuit devices formed in such a copper-containing silicon substrate.
However, a silicon substrate is normally provided with a roughened surface on the back side of the substrate which prevents easy removal of accumulated copper thereon. Such a roughened back surface is normally provided to facilitate differentiation between the front and back sides of the substrate during processing. The roughened back surface of the substrate also serves to create strain fields in the back surface of the substrate which act as a gettering surface for minor metal impurities in the silicon substrate, such as Cr, Ni, Fe, Ca, and Cu. Such minor impurities diffuse to the surface of the silicon substrate during high temperature processing of the substrate to form the integrated circuit devices therein. While such strain fields might be expected to mitigate undesired diffusion of copper into and through the silicon substrate (by tying up the copper atoms), it is believed that the amount of copper which may be expected to accumulate on the back surface of the substrate during a CVD or electroplating copper deposition process may be in excess of the amount of copper which may be effectively gettered by the roughened back surface of the substrate.
It is conventional to mechanically grind the backside of a silicon substrate after all processing of the front side of the substrate is completed, both to thin the substrate thickness, as well as to ensure uniformity of substrate thickness which facilitates subsequent packaging. While such grinding would remove any copper deposited on the back surface of the substrate, by the time this grinding step is carried out--at the end of all processing, copper already deposited on the back surface of the substrate during earlier metal interconnects forming steps, may have already had an opportunity to diffuse into the substrate during heating steps performed on the substrate subsequent to the copper deposition and prior to this wafer thinning step.